In recent years, a performance of a component that is applied to a computer or an information processing apparatus other than the computer has been significantly improved. For example, there has been a remarkable improvement in performance of a semiconductor memory device such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), and a central processing unit (CPU) or a large scale integration (LSI) for a switch.
Thus, with the improved performance of the semiconductor memory device or the processor, if a signal transmission speed between components or configuration elements is not improved, a point is reached where it is difficult to improve a system performance.
That is, improvement of a signal transmission speed is important between a main storage device such as a DRAM and a processor, between servers via a network or between boards (printed wiring substrate), between semiconductor chips, or between elements or circuit blocks in one chip.
However, for example, in order to speed up the signal transmission, it is preferable that a serial transmission method which may remove skew between bits caused by a wire length difference that is a problem in a parallel transmission method, be applied.
Specifically, a communication speed of a circuit (for example, serializer and deserializer (SerDes):parallel-serial conversion circuit) that transmits and receives data at a high speed reaches several tens of Gbps.
Then, Ethernet (registered trademark) already uses a transmission standard of 25 Gbps, and furthermore, standardization of 40 Gbps or 56 Gbps (for example, CEI-56G-VSR) is also progressing.
In addition, in recent years, for example, for a high speed I/O (receiver and communication device), both an increase of transmission speed×the number of channels, and a low power consumption have been demanded. For this reason, for example, a high speed I/O transmits clocks of a low frequency output from a clock generator, and generates multi-phase clocks using a delay locked loop (DLL) or an injection locked voltage controlled oscillator (IL-VCO), in the channels of each transmitter and each receiver.
Furthermore, the phases of the generated multi-phase clocks are adjusted by a phase interpolator (PI) that is controlled by a phase code from a clock data recovery (CDR).
Then, by frequency-multiplying the multi-phase clocks, phases of which are adjusted, clocks of a desired high frequency are generated, and the clocks are distributed to a multiplexer (MUX) in a transmitter, or a determination unit or a demultiplexer (DMX) in a receiver. Thus, it is possible to realize a signal transmission with a low power consumption at a high speed.
However, in recent years, various receivers (communication devices) which may perform a correct data transmission and receipt even in a high data transmission rate have been proposed.
As described above, for example, a high speed I/O provides a configuration that may perform a signal transmission with a low power consumption and a high speed. In addition, a latest high speed I/O (receiver) demands a configuration that includes not only a high speed function, but also interoperability with a high speed I/O of a previous generation, and that corresponds to a plurality of data rates with frequencies different from each other by two times or more.
For this reason, for example, sensitivity of a DLL is increased and the increased sensitivity corresponds to a wide range of clock frequency, or a variable capacitor for securing linearity of the PI that is provided in a receiver is provided. However, in such correspondence, if the sensitivity of the DLL is increased, for example, the frequency deviates even with respect to a small variation in a control voltage of the DLL, or if a capacitor is added to the PI, a frequency band is limited.
That is, for example, in order to correspond to the plurality of data rates with frequencies different from each other by two times or more, if the configurations of the DLL or the PI are changed, a clock performance at a high frequency band such as several GHz or higher is lower, which is not desired.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2009-239768,    [Document 2] Japanese Laid-open Patent Publication No. 2011-223366,    [Document 3] Japanese Laid-open Patent Publication No. 2012-054720, and    [Document 4] Japanese Laid-open Patent Publication No. 2012-147195.